Welcome to Sys-Inventor Lab!

Brief Biography

Lei Liu is an Associate Professor of Computer Science at Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), where he leads the Sys-Inventor Lab, which is a part of the State Key Lab of Computer Architecture. He joined the ICT faculty in 2014 after receiving his Ph.D. degrees in computer science from ICT (his Ph.D. thesis). Besides, he received his MS degree in software system design at University of Science and Technology of China (USTC), and BS degree in computer science at Dalian University of Technology (DLUT), respectively. He spent several years in industry as a software engineer and senior software architect. He was a visiting scholar in CS at the University of Rochester (UR).

He has led research projects that have advanced the Memory Systems, OS, Performance Isolation, and Profiling: 1) Technical evolutions for memory partitioning approaches; 2) Hybrid memory management in OS for systems using NVM-DRAM; and 3) Next generation OS - leveraging ML to build core components in OS. As the leading author, Lei has published research articles regarding the architecture and operating system in venues that include ISCA, PACT, IEEE TC, TPDS, ACM TACO, ICCD, and others. Recently, his work has focused on the intersection of the hybrid memory system (DRAM-NVM), OS for emerging technologies (including GPU, Graph, Quantum Computing as well as AI).

Lei Liu is an IEEE and ACM member, has served as the PC/ERC members, chairs for a number of main stream conferences (e.g., MICRO, HPCA, SC, PACT, ICS, IISWC, ISCA, ASPLOS, ICCD, ICPP, IPDPS, HPCC, General co-Chair of IEEE IISWC-2020, ACM ICS-2018) and reviewer for well-known Transactions (ACM TACO, ACM JETC, ACM TECS, ACM TRTS, IEEE TPDS). He received a number of awards.

His e-mail is: lei.liu@zoho.com; liulei2010@ict.ac.cn


刘磊的研究领域包括现代操作系统、新型内存系统、体系结构及可扩展性、系统性能评测等多个方面。自2011年起,刘磊带领其课题组在面向多核平台的操作系统、内存资源的利用率、访存优化机制等方向开展了一系列研究,并主导研发了面向主流多核、多通道服务器,及异构存储体系的内存资源管理系统原型。刘磊的研究成果以第一作者并通讯作者发表于ISCA, PACT, IEEE TC, TPDS, ACM TACO, ICCD等领域内权威学术会议和刊物,并在业内产生了影响力。近十年,刘磊曾主持或参与多项国家级项目(包括863、973、自然科学基金、重点研发计划等横纵项目,总计超1700余万元);此外,他还担任了一系列权威国际学术会议的程序委员会委员、外部评审委员、组委会成员,及学术期刊的审稿人40余次(并3次担任ACM/IEEE权威学术会议的总主席)。刘磊曾获得 “中国科学院院长优秀奖”、“国家奖学金”、“国科大优秀毕业生”、“计算所优秀科研人员” 等荣誉。


Sys-Inventor Lab - Next-Generation Clould Native Technologies

The research in Sys-Inventor Lab focuses on new strategies for next-generation Cloud native technologies, covering the interaction of OS, emerging applications and hardware. Our Research Interests include:

  • New Trend, AI and Quantum Computer
  • New Memory Architecture, e.g., NVM, Near Memory Computing, Memory Management and Optimization
  • New Operating System, OS for Emerging Technologies and Applications
  • Architectural Interaction and Resource Scheduling
  • Profiling and Performance Evaluation

Projects - Building Next-Generation Cloud Systems

  1. Next-Generation OS - Leveraging AI to Enhance the OS Design and Build Core Mechanisms

    News - On 26/Nov, 2019, the technique report about our first step study (OSML) is available via this Link.

  2. Quantum Computing Systems for Cloud

    News - On 25/April, 2020, the technique report - “A New Qubits Mapping Mechanism for Multi-programming Quantum Computing” - is available via this Link.

  3. Memory Management for Large Memory Systems

    Now, the memory system has much larger capacity than ever before. The virtual and physical address translation brings significant overheads at runtime in large memory systems. The Huge page mechanism is proposed to reduce the TLB misses and benefit the overall system performance. However, using huge pages might incur expensive memory compaction operations due to memory fragmentation problem, and lead to memory bloating. We propose SysMon-H, a sampling module in the OS kernel, which can obtain huge page utilization in a low overhead for both cloud and desktop applications. Furthermore, we propose H-Policy, a huge page management policy, which splits the underutilized huge pages to mitigate the memory bloating or promotes the base 4KB pages to huge pages based on the information provided by SysMon-H. The idea and first step effort are in ACM SIGOPS APSys-2019.

  4. Non-Volatile Memory - Hybrid Memory Management for Tiered Memory Systems in OS

    The emerging hybrid DRAM-NVM architecture is challenging the existing memory management mechanism in operating systems. In this project, we introduce Memos, which can hierarchically schedule memory resources over the entire memory hierarchy including cache, channels, main memory comprising DRAM and NVM simultaneously. Powered by our newly designed kernel-level monitoring module (HyMM) and page migration engine, Memos can dynamically optimize the data placement at the memory hierarchy in response to the on-line memory patterns, current resource utilization and memory medium features. The efforts are published in IEEE TPDS-2019 and ICCD-2016.

  5. Sysmon (2014~Now)

    A light-weight OS-level system monitoring tool suite, which is able to profile the memory utilization (including cache utilization, memory footprint, approximate row-buffer locality, physical page level logic re-use time, access frequency, hot/cold features and write/read patterns) without any hardware supports. SysMon is especially useful in VM and system-level research work. Sysmon is now open source on Github. The beta version is introduced in ISCA-2014, TC-2016, and we further discuss reducing the sampling overhead in APPT-2017 in detail.

  6. Hierarchically Optimizting Data Placement across Cache and Memory Banks on Cloud Servers (2013~Now)

    To provide ideal overall system throughput and QoS, in this project, the “Vertical Partitioning” is proposed to cooperatively optimize the data placement across cache and DRAM banks. We redesign the memory management component is OS kernel (e.g. buddy system) according to memory architecture details, thus “Vertical Partitioning” can simultaneously mitigate/eliminate the memory interferences at the entire memory hierarchy (i.e. cache-bank). Moreover, we further devise the “Curve-Vertical” Partitioning approach to handle the diverse memory behaviors exhibited by the appearing “memory-diversity” workloads on multi-core platforms. The efforts are published in ISCA-2014 and IEEE TC-2016 (Featured article invited).

  7. Reducing Memory Conflicts on Real Cloud Servers - DRAM Bank/Channel Partitioning Mechanism (BPM/BPM+) (2011~Now)

    This work begins with the contention/interference issues in main memory systems, and I tackle them from the Operating System angle. In existing OS, memory resources are “blindly” allocated to applications (threads), leading to memory contentions in DRAM Banks in the root. In order to solve this problem, I extend the well-known Page-Coloring to eliminate/mitigate the interferences between threads on memory banks and channels. These studies help and motivate many works on improving the overall system throughput, locality and QoS. More details are in PACT-2012 and ACM TACO-2014.

    - We are glad to see these efforts from Sys-Inventors have had impact on scientific community and industry.


  1. A New Qubits Mapping Mechanism for Multi-programming Quantum Computing (early version) [Slides (pptx)]

    Xinglei Dou, Lei Liu*. The 29th ACM/IEEE Intl. Conf. on Par. Architectures and Compilation Tech. (PACT):2020 (Poster)

  2. QoS-Aware Resources Scheduling for Microservices: A Multi-Model Collaborative Learning-based Approach

    Sys-Inventor Technical Report (PI: Lei Liu):2020

  3. An Analysis for Evolution of Memory Partitioning Technologies: Perspective, Opportunities and Methods

    Sys-Inventor Technical Report (PI: Lei Liu):2020

  4. Monitoring Memory Behaviors and Mitigating NUMA Drawbacks on Tiered NVM Systems [Slides (pptx)]

    S Yang, X Li, X Dou, X Gong, H Liu, L Chen, L Liu*. The 17th IFIP Intl. Conf. on Network and Par. Computing (NPC):2020

  5. Hierarchical Hybrid Memory Management in OS for Tiered Memory Systems

    Lei Liu*, Shengjie Yang, Lu Peng, Xinyu Li. IEEE Transactions on Parallel and Distributed Systems (TPDS):2019

  6. Architectural Support for NVRAM Persistence in GPUs

    Sui Chen, Lei Liu, Weihua Zhang, Lu Peng. IEEE Trans. on Par. & Dis. Sys. (TPDS):Accepted in 2019, to be appeared in 2020 Issue

  7. Efficient GPU NVRAM Persistence with Helper Warps

    Sui Chen, Faen Zhang, Lei Liu and Lu Peng. The 56th ACM/ESDA/IEEE Design Automation Conference (DAC):2019

  8. Thinking about A New Mechanism for Huge Page Management [Slides (pptx)]

    Xinyu Li, Lei Liu*, Shengjie Yang, Lu Peng, Jiefan Qiu. The 10th ACM SIGOPS Asia-Pacific Workshop on Systems (APSys):2019

  9. ACM Proceedings of the 2018 International Conference on Supercomputing, Beijing, China. June 12-15, 2018

    General co-Chair. ACM 32nd Intl. conf. on Supercomputing (ICS):2018

  10. Tackling Diversity and Heterogeneity by Vertical Memory Management

    Lei Liu. arXiv:1704.01198:2017 (Short Version for the ISCA-2014 Paper)

  11. Memos: Revisiting Hybrid Memory Management in Modern Operating System

    Lei Liu*, Mengyao Xie and Hao Yang. arXiv:1703.07725:2017

  12. SysMon: Monitoring Memory Behaviors via OS Approach

    Mengyao Xie, Lei Liu*, Hao Yang, Chenggang Wu, Hongna Geng. The 12th Intl. Symp. on Adv. Par. Processing Tech. (APPT):2017

  13. Memos: A Full Hierarchy Hybrid Memory Management Framework (Position Paper)

    Lei Liu*, Hao Yang, Mengyao Xie, Lian Li, Chenggang Wu. The 34th International Conf. on Computer Design (ICCD):2016

  14. Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random? [Slides (pptx)]

    Lei Liu*, Chen Ding, Hao Yang, Chengyong Wu. IEEE Transactions on Computers (TC):2016

    - Trans. Version of the ISCA-2014 paper. This article was a featured article candidate in IEEE TC.

  15. Going Vertical in Memory Management

    Lei Liu*, et al. ACM SIGARCH Computer Architecture News:October, 2014

  16. Going Vertical in Memory Management: Handling Multiplicity by Multi-policy [Slides (pptx)]

    Lei Liu*, et al. The 41st ACM/IEEE International Symposium on Computer Architecture (ISCA):2014 (acceptance rate: 17.8%)

    - The 9th ISCA paper in mainland China history since y2k.

  17. BPM/BPM+: Software-based Dynamic Memory Partitioning Mechanisms for Mitigating DRAM Bank-/Channel-level Interferences in Multicore Systems

    Lei Liu*, et al. ACM Transactions on Architecture and Code Optimization (TACO):2014

  18. A Software Memory Partition Approach for Eliminating Bank-level Interference in Multicore Systems [Slides (pptx)]

    Lei Liu*, et al. The 21st ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT):2012 (acceptance rate: 18.8%)

    - Influential Article in Semantic Scholar – Cited Greater than 200 Citations.

  19. WiseThrottling: A New Asynchronous Task Scheduler for Mitigating I/O Bottleneck in Large-Scale Datacenter Servers

    Fang Lv*, Lei Liu, Huimin Cui, Lei Wang, Ying Liu, Xiaobing Feng, P.C. Yew (UMN). J. of Supercomputing:2015

  20. Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

    Fang Lv*, Huimin Cui, Lei Wang, Lei Liu, Cheng-Gang Wu, Xiao-Bing Feng, and Pen-Chung Yew (UMN). JCST:2014

    Google Citation, * corresponding author


  1. Memory Resource Optimization Method and Apparatus (PCT, US). First Inventor (with Wu and Feng).

  2. 一种存储器资源优化方法和装置 (Chinese Version). First Inventor (with Wu and Feng). 发明人:刘磊、吴承勇、冯晓兵.

    - Part of the ideas in ISCA-2014 is within.


  1. 成功举办ACM ICS-2018(ACM ICS-2018 is successful! News in Chinese via ICT link

  2. 多核系统内存资源管理优化技术的研究(博士学位论文,导师:吴、冯;涵盖本人发表在ISCA、PACT、TACO的成果; Lei’s Ph. D. dissertation in Chinese, covering his work in ISCA, PACT and TACO. Supervisor: Wu and Feng)出版物链接(BOOK)

    Defense Committee (May/2014): Fengbin Qi (漆锋斌), Zhaoqing Zhang (张兆庆), Zifeng Hou (侯紫峰), Zhiyong Liu (刘志勇), Wenguang Chen (陈文光), Zhimin Tang (唐志敏), Xiaodong Zhang (张晓东)

  3. 编译技术的领路人-谨祝国重编译组张兆庆研究员获得“夏培肃奖”(Invited Essay in Chinese)

  4. PACT-2015 PC会议记录与硅谷工业界访问之行(Invited Essay in Chinese)

  5. ISCA-2014与北美学术之旅(Invited Essay in Chinese)

  6. Page Coloring的历史与发展(Invited Survey in Chinese)

Recent Professional Serivces

  1. General co-Chair of IEEE IISWC-2020, 2021
  2. General co-Chair of ACM ICS-2018 (Record attendance! and Record submission in recent 5 years!)
  3. Member of the Program Committee of MICRO-2020
  4. Member of the Program Committee of HPCA-2020
  5. Member of the Program Committee of IPDPS-2020
  6. Publicity co-Chair of IEEE IISWC-2019
  7. Member of the Program Committee of SC-2019
  8. Member of the Program Committee of ICCD-2018, 2019, 2020
  9. Member of the Program Committee of APPT-2019
  10. Member of the External Review Committee of HPCA-2019
  11. Member of the Program Committee of IISWC-2017
  12. Member of the Program Committee of ICPP-2017, 2020
  13. Member of the Program Committee of ICS-2017, and Chair of Session 5
  14. Member of the Program Committee of PACT-2015, 2016 (ERC), 2019 (ERC)
  15. Member of the External Review Committee of ISCA-2016
  16. Member of the Program Committee of IEEE IPDPS-2016
  17. Member of the Program Committee (ERC) of ASPLOS-2016, 2017, 2018 (Chair of Session Run time, and SRC Judge)
  18. Member of the Program Committee of HPCC-2015, 2016
  19. Member of the Program Committee of HP3C-2017, 2018, 2019
  21. Review Expert of National Science Foundation of China (NSFC)
  22. 《计算机工程》青年编委、审稿人

Recent News

  • Get a new funding from NSFC (2021~2024) for the research “An Investigation into the Key Technologies of Software Stack Design and Optimization for the Heterogeneous Memory and Computing Systems”. Congratulations to Sys-Inventors!
  • The first step effort on quantum computing is accepted as a poster by PACT-2020.
  • [Plz Note]: I am Lei Liu (刘磊 in Chinese); I have nothing to do with the Mulan project in ICT. The leader of this project has the same name in English but not with the same Chinese characters. Thanks for your understanding. More details on my work and myself can be found in this page. 请注意,我的名字是刘磊,我从未参与过“木兰”语言项目,研究领域也不是编程语言。该项目的负责人只是与我拼音名字相同而已。
  • We will host IEEE IISWC-2020, and I myself will serve as the chair in general for this event. Looking forward your contributions!
  • I am visiting LSU and College of William and Mary from 9~13/Dec 2019. The topic is “Achieving Better Resource Scheduling through Enhanced OS and ML Technologies”.
  • A paper from Sys-Inventor Lab is accepted by APSys-2019. The topic is on huge page management in OS.
  • Prof. Michael Scott visits us on 13/May, 2019. His talk is Systems Support for Persistent ‘In-Memory’ Data.
  • Looking forword your submissions to IEEE IISWC-2019.
  • A paper with the topic on hybrid memory management for DRAM-NVM from Sys-Inventor Lab is accepted by IEEE TPDS-2019. Congratulations!
  • A paper co-authored with Lu Peng’s group (the leading author was within) at LSU is accepted by DAC-2019.
  • Congratulations for the success of the ICS-2018. Thank people who contributed to this event. Prof. Mateo Valero’s Keynote slides and Prof. Hironori’s Keynote slides for ICS-2018 are avaiable here.
  • ICS-2018 is going to start tomorrow. Thanks for your coming!
  • Hope you could submit your excellent work to ICS-2018! Here is the CFP. Here is the Call for Workshop.
  • A paper is accepted in APPT-2017.
  • I am now visiting the CS department at U. of Rochester. cs.rochester.edu
  • ICS-2017 will be hold in Chicago. You are expected to submit your excellent work. Hope to see you there.:)
  • Lei Liu is promoted (1/33,14/15). Thank all of my friends. :)
  • A paper is accpeted in ICCD-2016, to appear at the conference in Phoenix, AZ, US.
  • [Good News]: ICS-2018 will be hold in Beijing, hosted by SKL, ICT, organized by Lei Liu, Michael Gschwind, Avi Mendelson, P-C Yew and Xiaobing Feng, etc. Come and join us, and let us make ICS a great success in China!
  • I will go to attend ICS-2016 from 1/June to 3, in Istanbul, and bid for ICS-2018, Beijing. Good Luck for all of our colleagues!
  • Best Wishes to all of my friends and collaborators! I wish you a very happy and fruitful new year, 2016, way to go!
  • Happy Teachers’ Day (教师节快乐) on 10/9/2015! I would like to extend my deep thanks to Prof. Zhang, Wu and Feng for their help in my Ph.D., and on behalf of professors in compiler team, I would like to extend our thanks to all of the students! You are the pride of us! Stay hungry, Stay foolish.
  • Our research entitled “An Investigation into Asymmetry Multi-Channel Architecture for Supporting Heterogeneous Memory System and the Corresponding Heuristic Memory Management Mechanism” will be supported by a new funding from Natural Science Foundation (NSF) of China from 2016 to the end of 2018. Congratulations to Sys-Inventors!
  • I am visiting VMware (CA,US) and Huawei research center (CA,US) from 27/July ~ 3/Aug 2015. The theme is “Rethinking Memory Management in Modern Operating System – Memory Optimization by Leveraging Hardware Features”.
  • Congratulations! The paper entitled “Rethinking Memory Management in Modern Operating System” from our Sys-Inventor group in Compiler team is Accepted by IEEE Trans. on Computers! Thank all of the authors for their contributions. On behalf of the authors in this paper, I would like to extend my deep thanks to these who pay attentions on our work for their valuable comments, especially Prof. Xiaodong Zhang (Ohio), P. C. Yew (UMN). This is a further step of our work in ISCA-2014, and more details of new findings are presented in this paper. You are expected to read it.
  • Hao Yang and Mengyao Xie joined us. Welcome!
  • I am visiting VMware in Palo Alto. CA US. (will give a talk about system optimization on 23 June 2014, Monday).
  • I go now to attend ISCA-2014 in MN US., and will present “Going Vertical in Memory Management” on 16 June Monday.
  • Congratulations! The paper “Going Vertical in Memory Management: Handling Multiplicity by Multi-policy” from our Sys-Inventor group in Compiler team was accepted by ISCA-2014.
  • Congratulations! The further work on DRAM Bank partitioning from Sys-Inventor, BPM/BPM+, was accepted by ACM TACO-2014.
  • Congratulations! The work on DRAM Bank partitioning from Sys-Inventor, was accepted by PACT-2012.

Awards and Honors

  • Outstanding Faculty Award, SKLCA, ICT, 2019
  • 100-Academic-Stars Program, ICT, 2017
  • Outstanding Scientific Researcher (Outstanding Faculty Award), ICT, 2015
  • National Scholarship for Ph.D
  • Chinese Academy of Sciences President’s Award for Excellence, Chinese Academy of Sciences
  • Outstanding Graduates, Chinese Academy of Sciences
  • Advanced Individual in State Key Lab. of Computer Architecture, ICT
  • The Bewinner Communications (北纬通信) Second Prize for Self-dependent Innovation
  • Merit student, Chinese Academy of Sciences

Academic Genealogy

Lei Liu Ph.D, 2014, ICT, CAS

Xiaobing Feng Ph.D, 1999, ICT, CAS; Chengyong Wu Ph.D, 2000 (He is a monk and has passed away. Mourns in memoriam)

Zhaoqing Zhang 1960, PKU

Resume References

Yunquan Zhang (ICT), Xiaobing Feng (ICT), Xiaowei Li (ICT), Guangyu Sun (PKU), Lu Peng (LSU), Bin Ren (WM), Scott Michael (Rochester), P-C Yew (UMN)


I’m fortunate to work or have worked with some of these brilliant ones, and also thank the former participants.

  • Shengjie Yang (B.S., Yunnan U.)
  • Xinyu Li (B.S., SJTU)
  • Zonghan Hua (ZJUT, co-Supervised w/ Prof. Jiefan Qiu)
  • Xinglei Dou (B.S., Jilin U.)
  • Xingxing Wu (B.S., Northwest A&F U.)
  • Yuetao Chen (B.S., Beijing Jiaotong U. - Weihai)

Former Students

  • Hao Yang, Master 2017, Huawei
  • Mengyao Xie, 9/2015~4/2018
  • Hongna Geng, 10/2016~4/2018

Recent and Former Collaborators

  • Lu Peng (LSU)
  • Chenliang Xu (UR)
  • Lingda Li (BNL)
  • P-C Yew (UMN)
  • Mingjie Xing (ICT)
  • Chenggang Wu (ICT)
  • Chen Ding (UR)
  • Fang Lv (Faculty, ICT)

— The below individuals were part-time workers in my project long time ago —

  • Yong Li (Engineer in VMware. Former participant from 2013~2015)
  • Zehan Cui (Within ICT till 2016. Former participant from 2011~2012)

Former Member

  • yungang Bao (Former member from 2011.11~2012 on early step writing work). 注:本研究组已于2013年起停止了与部分参与者的非正式合作,其并未真实参与本人2012-14年ISCA等工作。

*本课题组属于务实型课题组 - 实干兴邦,目的是培养富有想象力的实干派;本课题组与品行端正的科研工作者/学生合作,如有“务虚”、“走捷径”等想法,请绕行。


Postal Address

Address: 北京海淀区中关村科学院南路6号0612J (0612J, No.6, Kexueyuan South Road, Zhongguancun, Haidian District, Beijing, China)。

Post Code: 100190